Blog post #3 … the last one
As you can tell from the title, this will be my final blog post submission. I will be giving more details about the MCPU, as promised on my previous blog post which you can read here if you haven’t.
So let’s get started!
The Memory Tile
Illustrated above is the basic structure of the memory tile I worked on simulating using Coyote. The memory tile houses the MCPU (Memory Central Processing Unit), which can loosely be described as the ‘intelligence’ of the memory tile, responsible for organizing resources that are needed to perform the different memory operations.These resources are obtained from the microengine, the vector address generator (VAG) and within the MCPU itself. The microengine is responsible for generating transactions for the instructions, whereas the vector address generator generates the memory requests. Another impressive feature of this memory tile is that it allows the re-usability of some already implemented functionalities. For example, a scalar load operation is handled like a unit stride vector load with a loop iteration of 1.
My primary objective was to understand how instructions, commands and data packets are to be received into the memory tile. Once an overall understanding of the architecture was established, our goal was to simulate the different load and store operations (shown below) and analyse their output and performance.
Below is the video presentation my partner Aneta and I submitted for our project presentation. In it , we have discussed how the memory operations and scheduling processes are implemented in Coyote:
Before I leave …
The past two months have been the most exciting for me this year. I have had the opportunity to learn a lot from the internship and my able mentors. I have also established an interest in high-performance computing and I look forward to exploring this interest further in the near future. To you who is reading, I hope you enjoyed reading my blogs as much as I enjoyed writing them, and I also hope you learnt something new. I would like to thank my mentors at BSC, my partner Aneta, PRACE and you ,the readers for the guidance and support 🙂